Author: Dave Fang

High resolution TEM images from Hitachi

Jamie asked me to post these images of our membranes taken by Dr. Xiao Zhang from Hitachi.  They used a 300 kV tool to acquire these micrographs. The spacing between the atoms (striations) tells us the crystallographic orientation; most of

Posted in NRG

Pinhole study

Last week, five wafers were produced – three had a double 3500 A wet oxide growth/strip and two had a single 3500 A wet oxide growth/strip.  From Jess’ AFM work, an as-is wafer showed a high density of 5-7 nm

Posted in NRG

More on porosity vs. position

Last week I took a series of TEM images from all but one position on wafer 638.  Below are the TEMs, histograms, and porosities vs. distance from center plots.  “Xpos”, “xneg”, “ypos”, “yneg” indicate which axis the images were taken

Posted in NRG

Wafer 620: porosity vs. position

We’ve been assuming that porosity follows a linear relationship with respect to wafer position, but this turns out to be incorrect.  I imaged membranes from five points on wafer 620 and found that maximum porosity does not occur at the

Posted in NRG

Wafers 620/621

Today I etched wafer 621, which is the pair to 620.  While w620 has a relatively low pinhole density, w621 shows a much higher occurence of defects. Since the front-end processing and thermal treatment was identical for these wafers, I

Posted in NRG

WordPress updates

I’ve upgraded the WordPress publisher to version 2.6.  The most useful change is the ability to track changes to any post/page, compare revisions, and revert to an older version.  Here’s a video showing the changes: https://videopress.com/v/mARhRBcT/fmt_std Additionally, I’ve installed some

Posted in NRG

AJA membrane

While Chris and I were in Boston we deposited our membrane stack on a patterned wafer.  It was annealed at 1000 C and then etched.  Because we didn’t have an accurate deposition rate for Silicon, we overestimated and put down

Posted in NRG

Wafer 612 and 615

Wafer 612 was made to mimic wafer 504: 850 C RTP, cool down, 1000 C RTP.  Wafer 615 was annealed in two steps: first to 400 C and then to 1000 C (without inbetween cool down).  Both wafers showed a

Posted in NRG

Annealing w/o protective oxide

Here is a summary of results for membranes (w510X) that have been annealed without their protective oxide. 800 C RTP @ 10 C/s in susceptor 850 C RTP @ 10 C/s in susceptor 900 C RTP @ 10 C/s in

Posted in NRG

Two-step anneal trial

Last week I mentioned that a two step anneal may help with the tears that are forming on the membranes when they are annealed post-etch.  The recipe I used was a 10 C/s ramp to 600 C, hold 60 s,

Posted in NRG
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