We’ve been wondering about the effects of membrane stresses on discoloration rates.  This was spurred by Vlassak’s visit and his ideas about stress and membrane stability. In this experiment, I used w501, no RTP, in the oven in RPMI+10%FBS.  All…

Last week, I repeated Anant’s experiment which aimed to eliminate edge effects by painting over chips with nailpolish. I painted the entire well side of the chip but tried to keep the wells clear of polish (“painted back”) and I…

I got a couple of wafers from Chris last week – 50nm oxide deposited at room temperature or 450 degrees.  For each wafer, I saved the zsensor (top), phase (middle) and zsensor (bottom) scans.  I also calculated the roughness (the…

First off – OK now on to the science. Wafer 747 has a huge amount of pinholes, and in this study I wanted to see how these pinholes would effect electroosmosis.  I will show results here from two experiments with…

I wanted to do some more fluroescent imaging in transwells to look into background fluroescence.  This was mainly motivated by my inital study.  These are HUVECs stained with 5uM CMFDA and 10uM Hoechst 33342, fixed in formaldehyde and imaged on…

I did an experiment earlier this week in the Sepcon and flat format. I intentionally broke membrane windows so that I could compare chips with no intact membranes vs. chips with 1 intact membrane (and also the effect of autoclaving).…

Last week we attempted to mimic our standard CVC recipe in the AJA system (15 nm Si, 450 C deposition temp, 1000 C RTP).  I should note that the protective oxide thickness in the AJA membrane was 20 nm (not…

The image below was taken with UR’s new S/TEM, the FEI Technai F20.  It has the capability of resolving lattice images which should benefit the materials development effort.  However, we will still rely on Karen’s TEM for most of our…